Attempts continue to shrink the dimensions for fabricating metal oxide semiconductor (MOS) transistors. Devices having sub-micrometer dimensions permit closer placement of devices, thereby increasing the density of devices on a chip and also increasing device operating speed.
A conventional MOS transistor which is formed in a semiconductor substrate includes a drain region and a source region separated by a channel region. The channel region resides beneath a gate comprising a gate oxide and a gate electrode formed thereon. A conducting channel is induced in the channel region by an electric field established between the gate and the semiconductor substrate.
To fabricate an MOS transistor, the drain region and the source region are formed in the semiconductor substrate, which has a first conductivity (e.g., p-type), by doping selected regions of the semiconductor substrate. Doping is performed such that the drain region and the source region have a second conductivity (e.g., n-type) that is opposite to the first conductivity. In the case where the semiconductor substrate comprises silicon, the gate electrode and the gate oxide may comprise, for example, polysilicon ("poly") and silicon dioxide, respectively.
Hot-carrier degradation is a major limitation of scaling down the dimensions of MOS devices; hot-carrier degradation results from the high electric fields encountered in submicrometer MOSFETs. Although an energy barrier separates the gate oxide from the semiconductor substrate, electrons (known as"hot carriers") that have enough energy to overcome this energy barrier are injected into the gate oxide. The injection of these"hot carriers" causes damage to the gate oxide, which affects the performance of the MOS device. Hot-carrier degradation refers to the performance degradation that results from this damage to the gate oxide.
Hot-carrier degradation is reduced by the structure of lightly doped drain (LDD) transistors. The key feature of LDD technology is the insertion of a graded, or more gently profiled, lightly doped drain region, such as an n.sup.- drain region, between the channel region and a heavily doped part of the drain region, such as an n.sup.30 drain region. As is conventional, the term"drain" may be used generically and can apply to both the drain and the source. Accordingly, in LDD transistors, a graded, or more gently profiled, lightly doped source region, such as an n.sup.31 source region, is inserted between the channel region and a heavily doped part of the source region, such as an n.sup.30 source region. The source-side LDD is formed simultaneously with the drain-side LDD. A voltage is sustained mainly across the drain-side LDD. The lightly doped drain region sustains the drain voltage over a longer area. Similarly, the lightly doped source region sustains a source voltage over a longer area. Thus, the peak electric field at the drain region and source region is reduced.
There are many types of LDD transistors presently in use which reduce the hot-carrier degradation inherent in MOSFETs. For example, performance degradation due to hot carrier damage in MOS transistors can be improved by making LDD regions (i.e., the lightly doped drain region and the lightly doped source region) fully overlapped by the gate electrode. Such an approach is demonstrated by gate over-lapped drain (GOLD) structures as well as inverse-T gate LDD (ITLDD) structures. These conventional fully overlapped LDD structures, however, suffer from a high capacitance between the gate and drain region as well as between the gate and source region. Such capacitance is conventionally known in the art as drain-to-gate overlap capacitance. In conventional fully overlapped LDD structures, the drain-to-gate overlap capacitance typically corresponds to the value of capacitance across the gate oxide. This value of capacitance depends on the thickness of the gate oxide. Disadvantageously, a high drain-to-gate overlap capacitance can seriously limit AC circuit performance.
Thus, what is needed is an improved MOSFET structure that employs LDD regions that are fully overlapped by gate polysilicon but that has a drain-to-gate overlap capacitance significantly reduced in comparison to conventional fully overlapped LDD transistors.